<?xml version="1.0" encoding="utf-8" standalone="yes"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom">
  <channel>
    <title>Tech on Nalar</title>
    <link>https://nalar.dev/categories/tech/</link>
    <description>Recent content in Tech on Nalar</description>
    <generator>Hugo</generator>
    <language>en-us</language>
    <lastBuildDate>Wed, 16 Sep 2026 00:00:00 +0700</lastBuildDate>
    <atom:link href="https://nalar.dev/categories/tech/index.xml" rel="self" type="application/rss+xml" />
    <item>
      <title>PCIe Active State Power Management Trades Idle Power for Exit Latency</title>
      <link>https://nalar.dev/pcie-active-state-power-management-trades-idle-power-for-exit-latency/</link>
      <pubDate>Wed, 16 Sep 2026 00:00:00 +0700</pubDate>
      <guid>https://nalar.dev/pcie-active-state-power-management-trades-idle-power-for-exit-latency/</guid>
      <description>&lt;p&gt;A PCI Express link does not need to stay at its fully active electrical state while no traffic is moving. Active State Power Management, commonly shortened to ASPM, lets compatible link partners place the link into lower-power states during idle periods.&lt;/p&gt;&#xA;&lt;p&gt;The practical tradeoff is simple: deeper idle states can save more power, but returning to active operation takes time. That exit delay becomes part of the latency seen when new traffic arrives.&lt;/p&gt;</description>
    </item>
    <item>
      <title>PCIe Relaxed Ordering Lets Transactions Pass Within Ordering Rules</title>
      <link>https://nalar.dev/pcie-relaxed-ordering-lets-transactions-pass-within-ordering-rules/</link>
      <pubDate>Wed, 16 Sep 2026 00:00:00 +0700</pubDate>
      <guid>https://nalar.dev/pcie-relaxed-ordering-lets-transactions-pass-within-ordering-rules/</guid>
      <description>&lt;h1 id=&#34;pcie-relaxed-ordering-lets-transactions-pass-within-ordering-rules&#34;&gt;PCIe Relaxed Ordering Lets Transactions Pass Within Ordering Rules&lt;/h1&gt;&#xA;&lt;p&gt;PCI Express carries requests and completions through switches, bridges, and endpoint logic that can have several transactions in flight at once. Strict ordering between every packet would make many independent transfers wait behind traffic that has no dependency on them. Relaxed Ordering provides a protocol signal that permits more reordering where the requester can tolerate it.&lt;/p&gt;&#xA;&lt;p&gt;The feature does not remove all ordering constraints. It marks a transaction as eligible for additional movement relative to other traffic, while PCIe ordering rules still define which combinations may pass. Software and device logic must only use the attribute when reordering cannot expose stale state or break a producer-consumer dependency.&lt;/p&gt;</description>
    </item>
    <item>
      <title>USB Selective Suspend Reduces Power for Idle Devices</title>
      <link>https://nalar.dev/usb-selective-suspend-reduces-power-for-idle-devices/</link>
      <pubDate>Wed, 16 Sep 2026 00:00:00 +0700</pubDate>
      <guid>https://nalar.dev/usb-selective-suspend-reduces-power-for-idle-devices/</guid>
      <description>&lt;p&gt;USB does not require every attached device to remain fully active whenever the computer is running. A host can suspend an idle USB device while other devices continue transferring data.&lt;/p&gt;&#xA;&lt;p&gt;This behavior reduces unnecessary power use, especially on portable systems with several peripherals. The useful distinction is scope: selective suspend targets an idle device or interface rather than treating the entire USB controller as one power unit.&lt;/p&gt;&#xA;&lt;h2 id=&#34;suspend-applies-to-idle-usb-activity&#34;&gt;Suspend applies to idle USB activity&lt;/h2&gt;&#xA;&lt;p&gt;A USB host schedules transfers. When a device has no useful work pending, keeping all of its circuitry active can waste energy.&lt;/p&gt;</description>
    </item>
  </channel>
</rss>
