An ESP32 audio configuration can look deceptively similar to ordinary GPIO setup:

const uint8_t I2S_MCLK = 0;
const uint8_t I2S_SCK = 5;
const uint8_t I2S_WS = 25;
const uint8_t I2S_SDOUT = 26;
const uint8_t I2S_SDIN = 35;

These constants do not define five interchangeable audio wires. Each represents a different part of the I2S timing and data path. A speaker amplifier can remain completely silent even when every GPIO is electrically connected if BCLK and WS are missing, the data direction is reversed, or the frame format does not match the receiving device.

The useful way to read an I2S pin map is as a signal-routing diagram.

I2S separates clocks from audio data

In standard I2S, the audio samples travel on a serial data line while separate clock signals tell the receiver when each bit and each channel begins.

A typical ESP32 master connection looks like this:

                    BCLK
ESP32  --------------------------------> audio device

                     WS
ESP32  --------------------------------> audio device

                    DOUT
ESP32  --------------------------------> DAC / amplifier

                     DIN
ESP32  <-------------------------------- digital microphone

                    MCLK
ESP32  --------------------------------> codec, if required

The arrows matter. DOUT and DIN are named from the ESP32’s point of view. DOUT is data leaving the ESP32. DIN is data entering it.

That means a MAX98357A digital amplifier belongs on the transmit path, while an INMP441 microphone belongs on the receive path.

BCLK clocks individual audio bits

A definition such as:

const uint8_t I2S_SCK = 5;

usually means GPIO 5 carries the I2S bit clock. Libraries and datasheets use several names for this signal, including BCLK, BCK, and SCK.

Each BCLK edge advances the serial audio stream by one bit. Its frequency therefore depends on the sample rate, the number of slots in each frame, and the slot width.

For a conventional stereo frame with two 32-bit slots at 48 kHz:

BCLK = 48,000 × 2 × 32
     = 3,072,000 Hz

The audio sample rate is 48 kHz, but the bit clock is 3.072 MHz because every frame contains 64 serial bit positions.

This distinction becomes important with the INMP441. Its I2S interface produces 24-bit two’s-complement samples, but its bus timing requires 32 SCK cycles per channel and 64 SCK cycles per stereo frame. Configuring the receiver around only the 24 meaningful sample bits can therefore produce the wrong frame timing.

WS identifies the audio slot

const uint8_t I2S_WS = 25;

assigns GPIO 25 to word select. The same signal is commonly called WS, LRCLK, LRCK, or left/right clock.

In standard stereo I2S, WS separates the two channel slots. Its frequency is normally the audio sample rate:

sample rate = 48 kHz
WS frequency = 48 kHz

WS does not carry the audio itself. It establishes which slot is currently being transmitted.

This is especially relevant to a mono I2S microphone such as the INMP441. Its L/R pin selects whether the microphone drives the left or right slot. Software must read the corresponding slot. Reading the opposite slot can look like a dead microphone even though BCLK, WS, and the microphone itself are operating.

SDOUT sends PCM samples to the amplifier

const uint8_t I2S_SDOUT = 26;

means GPIO 26 is the ESP32’s serial audio output.

For a MAX98357A, the connection is conceptually:

ESP32 I2S_SDOUT (GPIO 26) ---> MAX98357A DIN
ESP32 I2S_SCK   (GPIO 5)  ---> MAX98357A BCLK
ESP32 I2S_WS    (GPIO 25) ---> MAX98357A LRCLK

The naming can cause confusion because one side says DOUT and the other says DIN. That is correct: the ESP32 output connects to the amplifier input.

The MAX98357A accepts standard I2S through DIN, BCLK, and LRCLK. It supports 16-, 24-, and 32-bit I2S data and sample rates from 8 kHz to 96 kHz. It does not require an external MCLK.

That last property is useful when diagnosing a silent MAX98357A. Adding an MCLK wire is not the first fix for this device; valid BCLK, LRCLK, DIN data, power, shutdown/channel configuration, and speaker wiring are more relevant checks.

SDIN receives samples from a digital microphone

const uint8_t I2S_SDIN = 35;

assigns GPIO 35 as the serial input in this particular board configuration.

For an INMP441:

INMP441 SD  ---> ESP32 I2S_SDIN
ESP32 BCLK  ---> INMP441 SCK
ESP32 WS    ---> INMP441 WS

The microphone is an I2S slave. The ESP32 supplies SCK and WS, and the microphone places sample bits onto SD.

The INMP441 sends a 24-bit, two’s-complement, MSB-first sample in standard I2S format. Standard I2S delays the most significant data bit by one clock after the channel boundary. That detail is why selecting the correct Philips/I2S format in the ESP-IDF driver matters; an MSB-justified configuration describes different timing.

MCLK is not universally required

const uint8_t I2S_MCLK = 0;

means GPIO 0 has been assigned to master clock in this configuration. It does not mean that every connected I2S device must use that signal.

MCLK is a higher-frequency reference clock used by some codecs and converters to run internal processing. ESP-IDF treats MCLK as an optional I2S signal because the requirement belongs to the peripheral device.

A bus can therefore legitimately look like this:

ESP32
  |
  +-- BCLK ----> MAX98357A
  +-- WS ------> MAX98357A
  +-- DOUT ----> MAX98357A
  |
  +-- BCLK ----> INMP441
  +-- WS ------> INMP441
  +<-- DIN ----- INMP441

with no MCLK connection to either of those devices.

The correct rule is not “I2S needs MCLK” or “I2S never needs MCLK.” Check the clock requirements of the specific slave.

I2C pins are unrelated to the PCM stream

The same project may also contain:

const uint8_t I2C_SCL = 23;
const uint8_t I2C_SDA = 18;
const uint32_t I2C_FREQ = 400000;

These definitions describe an I2C bus, not the I2S audio path.

SCL is the I2C clock, SDA is the bidirectional data line, and 400000 configures a 400 kHz bus rate. Audio codecs often use I2C for control registers while I2S carries the actual PCM samples, which is why both interfaces can appear in the same audio project.

Their jobs remain separate:

I2C
SCL + SDA
    |
    +--> configuration, registers, control

I2S
MCLK/BCLK/WS + DIN/DOUT
    |
    +--> digital audio samples

Neither the MAX98357A nor INMP441 requires an I2C control connection for its basic audio data path.

Full-duplex I2S requires matching frame timing

ESP-IDF can allocate TX and RX channels together on one I2S controller. When those channels operate as full duplex and share BCLK and WS, their frame timing must agree.

This is more restrictive than merely choosing the same sample rate. The total number of bits per frame determines BCLK.

For example:

RX: 48 kHz × 2 slots × 32 bits = 3.072 MHz BCLK
TX: 48 kHz × 2 slots × 16 bits = 1.536 MHz BCLK

Those are not the same bus timing.

A microphone-to-speaker loopback can therefore fail when RX is configured as 32-bit stereo and TX as 16-bit stereo while both are expected to behave as one synchronous full-duplex bus. One solution is to use compatible slot timing on the shared bus and convert sample precision in software. Another is to use independent I2S controllers or independent clocks when the hardware architecture requires different timing.

The sample representation in memory and the number of clock periods on the wire are related, but they are not concepts that should be changed independently without checking the resulting frame.

Debug a silent speaker from the output backward

When testing a MAX98357A, feeding microphone data through the entire pipeline creates too many possible failure points. A deterministic PCM signal is a better first test.

The diagnostic path is:

known PCM samples
      |
      v
ESP32 TX buffer
      |
      v
I2S DOUT + BCLK + WS
      |
      v
MAX98357A
      |
      v
speaker

A generated sine wave removes Wi-Fi, HTTP streaming, MP3/AAC decoding, microphone slot selection, microphone gain, and RX conversion from the test.

Once that signal produces sound, add the receive side:

INMP441
   |
   v
I2S RX
   |
24/32-bit sample conversion
   |
   v
I2S TX
   |
   v
MAX98357A

Online radio belongs later in the sequence. A radio stream adds networking, buffering, container handling, and usually compressed-audio decoding before PCM ever reaches I2S. Silence at that stage does not isolate the amplifier.

Pin numbers are board configuration, signal roles are protocol behavior

The most important distinction in an ESP32 audio pin table is between the physical GPIO number and the I2S signal assigned to it.

GPIO 5  -> BCLK
GPIO 25 -> WS
GPIO 26 -> DOUT
GPIO 35 -> DIN
GPIO 0  -> MCLK, if used

Those GPIO numbers describe one hardware design. The meanings of BCLK, WS, DOUT, DIN, and MCLK describe the bus.

When an audio path is silent, debugging the signal roles first is usually more productive than changing sample rates or gain at random. Confirm that the ESP32 is generating the expected clocks, that data flows in the correct direction, that the selected I2S format and slot match the peripheral, and that TX and RX frame timing is compatible. Once those conditions are correct, higher-level audio processing has a reliable transport underneath it.

ESP32 I2S Digital Audio MAX98357A INMP441