https://nalar.dev/tags/device-i/o/ Recent content in Device I/O on Nalar Hugo en-us Mon, 01 Jan 0001 00:00:00 +0000 https://nalar.dev/pcie-posted-mmio-writes-readback-completion/ Sat, 19 Sep 2026 00:00:00 +0000 https://nalar.dev/pcie-posted-mmio-writes-readback-completion/ <p>A CPU can retire or complete an MMIO store before the corresponding PCIe Memory Write has reached the target device. The gap exists because PCIe Memory Write requests are posted: the requester sends them without waiting for a completion packet from the completer.</p> <p>That property is useful for throughput, but it creates an important boundary. A software-visible store instruction, an ordering barrier, and device observation of the write are not automatically the same event.</p>