https://nalar.dev/tags/mmio/ Recent content in MMIO on Nalar Hugo en-us Sat, 19 Sep 2026 00:00:00 +0000 https://nalar.dev/pcie-posted-mmio-writes-readback-completion/ Sat, 19 Sep 2026 00:00:00 +0000 https://nalar.dev/pcie-posted-mmio-writes-readback-completion/ <p>A CPU can retire or complete an MMIO store before the corresponding PCIe Memory Write has reached the target device. The gap exists because PCIe Memory Write requests are posted: the requester sends them without waiting for a completion packet from the completer.</p> <p>That property is useful for throughput, but it creates an important boundary. A software-visible store instruction, an ordering barrier, and device observation of the write are not automatically the same event.</p> https://nalar.dev/write-combining-device-memory-can-merge-cpu-stores-before-io/ Sat, 19 Sep 2026 00:00:00 +0000 https://nalar.dev/write-combining-device-memory-can-merge-cpu-stores-before-io/ <h1 id="write-combining-device-memory-can-merge-cpu-stores-before-io">Write-Combining Device Memory Can Merge CPU Stores Before I/O</h1> <p>A sequence of CPU stores to device memory does not necessarily become an identical sequence of bus transactions. With a write-combining mapping, the processor may collect adjacent stores and emit a larger transfer later. That behavior suits framebuffer-like regions and other device buffers built for bulk writes, but it changes the ordering and transaction assumptions a driver can safely make.</p> <p>Linux exposes this mapping class through interfaces such as <code>ioremap_wc()</code>. It is distinct from the default <code>ioremap()</code> mapping used for ordinary control registers.</p>