NVMe on Nalar

NVMe Queues Let Storage Handle Many Commands in Parallel

Tue, 15 Sep 2026 00:00:00 +0700

NVMe storage does not send every read or write through one shared command line. The protocol is built around queue pairs: software places commands into a submission queue, and the controller reports finished work through a corresponding completion queue.

That structure matters most when several processor cores and application threads are generating storage work at the same time. Multiple queues can distribute command handling across cores, reduce contention around a single software path, and keep a fast solid-state drive supplied with enough outstanding work.

SSD TRIM Marks Discarded Data for Flash Reuse

Tue, 15 Sep 2026 00:00:00 +0700

Deleting a file changes filesystem metadata, but that action does not automatically tell a solid-state drive which flash pages no longer contain useful data. From the drive’s point of view, previously written logical block addresses can remain valid until the host explicitly replaces them or marks them as discarded.

TRIM closes that information gap. The operating system can notify the storage device that selected logical blocks no longer need their old contents. The SSD may then treat the associated data as disposable during its internal space-management work.

NVMe APST Moves Idle SSDs Into Lower Power States

Mon, 14 Sep 2026 00:00:00 +0700

An NVMe SSD can support several power states rather than operating at one fixed power level. Active states favor quick access and throughput, while deeper idle states can reduce energy use at the cost of extra time needed to return to full activity.

Autonomous Power State Transition, commonly shortened to APST, lets the host configure automatic movement into selected lower-power states after defined idle periods. Once configured, the controller can perform those transitions without a separate host command for every idle event.